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fast page mode 4194304-bit (262144-word by 16-bit) dynamic ram m5m44260cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44260cj,tp-5,-5s : under development this is a family of 262144-word by 16-bit dynamic rams, fabricated with the high performance cmos process, and is ideal for memory systems where high speed, low power dissipation, and low costs are essential. the use of double-layer metalization process technology and a single-transistor dynamic storage stacked capacitor cell provide high circuit density at reduced costs. multiplexed address inputs permit both a reduction in pins and an increase in system densities. self or extended refresh current is small enough for battery back-up application. this device has 2cas and 1w terminals with a refresh cycle of 512 cycles every 8.2ms. 1 description features standard 40pin soj, 44 pin tsop (ii) single 5v?0% supply low stand-by power dissipation cmos input level 5.5mw (max) cmos input level 550? (max) * operating power dissipation m5m44260cxx-5,-5s 688mw (max) m5m44260cxx-6,-6s 605mw (max) m5m44260cxx-7,-7s 523mw (max) self refresh capability * self refresh current 150? (max) extended refresh capability extended refresh current 150? (max) fast-page mode (512-column random access), read-modify-write, ras-only refresh, cas before ras refresh, hidden refresh capabilities. early-write mode, lcas / ucas and oe to control output buffer impedance 512 refresh cycles every 8.2ms (a 0 ~a 8 ) 512 refresh cycles every 128ms (a 0 ~a 8 ) * byte or word control for read/write operation (2cas, 1w type) * : applicable to self refresh version (m5m44260cj,tp-5s,-6s,-7s : option) only xx=j,tp type name access time (max.ns) ras access time (max.ns) cas (max.ns) access time address time (min.ns) cycle dissipa- (typ.mw) power tion m5m44260cxx-7,-7s m5m44260cxx-6,-6s 60 70 15 20 30 35 110 130 550 475 15 20 access time (max.ns) oe m5m44260cxx-5,-5s 50 13 25 90 625 13 application microcomputer memory, refresh memory for crt pin configuration (top view) 1 9 2 3 4 5 11 10 12 13 40 39 38 37 36 30 32 31 29 28 dq 1 a 0 a 1 a 2 a 3 (5v)v cc v ss (0v) nc a 8 a 7 a 6 a 5 a 4 w ras ucas oe outline 40p0k (400mil soj) 6 7 8 35 34 33 16 18 17 19 20 14 15 25 23 24 22 21 27 26 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 8 (5v)v cc (5v)v cc nc nc lcas nc dq 12 dq 11 dq 10 dq 9 v ss (0v) dq 16 dq 15 dq 14 dq 13 v ss (0v) 1 9 2 3 4 5 13 10 14 15 44 43 42 41 40 32 36 35 31 30 dq 1 a 0 a 1 a 2 a 3 (5v)v cc v ss (0v) nc a 8 a 7 a 6 a 5 a 4 w ras ucas oe outline 44p3w-r (400mil tsop nomal bend) 6 7 8 39 38 37 18 20 19 21 22 16 17 27 25 26 24 23 29 28 dq 2 dq 3 dq4 dq 5 dq 6 dq 7 dq 8 (5v)v cc (5v)v cc nc nc lcas nc dq 12 dq 11 dq 10 dq 9 v ss (0v) dq 16 dq 15 dq 14 dq 13 v ss (0v) nc: no connection fast page mode 4194304-bit (262144-word by 16-bit) dynamic ram m5m44260cj,tp-5,-6,-7, -5s,-6s,-7s mitsubishi lsis pin description pin name a 0 ~a 8 dq 1 ~dq 16 ras ucas w oe v cc v ss function address inputs data inputs / outputs row address strobe input upper byte control column address strobe input write control input power supply (+5v) ground (0v) output enable input lower byte control column address strobe input lcas
fast page mode 4194304-bit (262144-word by 16-bit) dynamic ram m5m44260cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44260cj,tp-5,-5s : under development row decoder row & column address buffer a 0 ~a 8 a 0 ~ a 8 (8)lower data in buffer (8)lower data out buffer (8)upper data in buffer (8)upper data out buffer 2 function in addition to normal read,write and read-modify-write operations the m5m44260cj, tp provides a number of other functions, e.g., table 1 input conditions for each mode fast page mode, ras-only refresh and delayed-write. the input conditions for each are shown in table 1. note : act : active, nac : nonactive, dnc : don' t care, opn : open operation lower byte read upper byte read word read lower byte write upper byte write ras only refresh self refresh * word write cas before ras (extended *) refresh ras lcas oe inputs input/output w dq 1 ~ dq 8 dq 9 ~ dq 16 act act act act act act act nac act nac act act nac act nac dnc nac nac nac act act act dnc dnc act act act nac nac nac dnc dnc d out opn d out d in dnc d in opn opn opn d out d out dnc d in d in opn opn act act dnc dnc opn opn stand-by act dnc dnc opn d out ucas nac act act nac act act nac dnc act act act hidden refresh act act act act d out opn row address column address apd apd apd apd apd dnc dnc dnc apd apd apd apd dnc dnc dnc dnc dnc dnc refresh remark dnc apd apd apd apd yes yes yes yes yes yes yes yes yes yes no fast page mode identical block diagram a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 address inputs clock generator circuit column decoder sense refresh amplifier & i /o control memory cell (4194304 bits) v cc (5v) v ss (0v) dq9 oe dq10 dq16 upper data inputs / outputs output enable input lower byte control column address strobe input row address strobe input write control input lcas w ras ucas upper byte control column address strobe input lower upper dq 1 dq 2 dq 8 lower data inputs / outputs v cc (5v) v ss (0v) v cc (5v) v ss (0v)
fast page mode 4194304-bit (262144-word by 16-bit) dynamic ram m5m44260cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44260cj,tp-5,-5s : under development 3 absolute maximum ratings symbol v cc v i v o i o p d t opr t stg parameter conditions ratings unit v v v ma mw -1~7 50 1000 0~70 -65~150 with respect to v ss ta=25?c supply voltage input voltage output voltage output current power dissipation operating temperature storage temperature -1~7 -1~7 recommended operating conditions unit limits min nom max v v v v 0 0.8 0 5.5 0 2.4 -0.5 * * parameter supply voltage supply voltage high-level input voltage, all inputs low-level input voltage, all inputs v cc symbol v ss v ih v il note 1 : all voltage values are with respect to v ss. 5.0 4.5 6.0 (ta=0~70?c, unless otherwise noted) (note 1) * * : v il(min) is -2.0v when pulse width is less than 25ns. (pulse width is with respect to vss.) note 2: current flowing into an ic is positive, out is negative. 3: i cc1 (av) , i cc3 (av) , i cc4 (av) , and i cc6 (av) are dependent on cycle rate. maximum current is measured at the fastest cycle rate. 4: i cc1 (av) and i cc4 (av) are dependent on output loading. specified values are obtained with the output open. 5: column address can be changed once or less while ras=v il and cas=v ih . electrical characteristics (ta=0~70?c , v cc =5v?0%, v ss =0v, unless otherwise noted) (note 2) symbol v oh v ol i oz i i i cc1(av) i cc2 i cc3(av) i cc4(av) i cc6(av) high-level output voltage parameter limits min max unit typ test conditions low-level output voltage off-state output current input current average supply current from vcc, operating (note 3,4,5) (note 3,5) (note 3,4,5) supply current from v cc , stand-by average supply current from vcc, ras only refresh mode average supply current from vcc fast page mode average supply current from vcc cas before ras refresh mode m5m44260c-5,-5s m5m44260c-6,-6s m5m44260c-7,-7s i oh =-5ma i ol =4.2ma q floating 0v v out 5.5v 0v v in +6.0v, other inputs pins=0v ras, cas cycling t rc =t wc =min. output open ras= cas =v ih , output open ras cycling, cas=v ih t rc =min. output open ras=v il , cas cycling t pc =min. output open cas before ras refresh cycling t rc =min. output open v v ma ma ma ma ma v cc 0.4 10 10 2 1.0 115 100 85 2.4 0 -10 -10 125 110 95 (note 6) 125 110 95 125 110 95 m5m44260c-5,-5s m5m44260c-6,-6s m5m44260c-7,-7s m5m44260c-5,-5s m5m44260c-6,-6s m5m44260c-7,-7s m5m44260c-5,-5s m5m44260c-6,-6s m5m44260c-7,-7s average supply current from v cc extended-refresh mode ? 150 average supply current from v cc self-refresh mode ras=cas 0.2v output open ? 150 (note 6) ras= cas 3 v cc -0.5v output open 0.1 * ? ? i cc8(av) * i cc9(av) * ras cycling cas 0.2v or cas before ras refresh cycling ras 0.2v or 3 v cc -0.2v cas 0.2v or 3 v cc -0.2v w 0.2v or 3 v cc -0.2v oe 0.2v or 3 v cc -0.2v a 0 ~a 8 0.2v or 3 v cc -0.2v, dq=open t rc =250?, t ras =t ras min ~1? (note 3,5) (note 6) ?c ?c
fast page mode 4194304-bit (262144-word by 16-bit) dynamic ram m5m44260cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44260cj,tp-5,-5s : under development 4 note 6: an initial pause of 500 ? is required after power-up followed by a minimum of eight initialization cycles (ras-only refresh or cas before ras refresh cycles). note the ras may be cycled during the initial pause. and 8 initialization cycles are required after prolonged periods (greater than 8.2ms) of ras inactivity before proper device operation is achieved. 7: measured with a load circuit equivalent to 2ttl loads and 100pf. 8: assumes that t rcd 3 t rcd(max) and t asc 3 t asc(max) . 9: assumes that t rcd t rcd(max) and t rad t rad(max) . if t rcd or t rad is greater than the maximum recommended value shown in this table, t rac will increase by amount that t rcd exceeds the value shown. 10: assumes that t rad 3 t rad(max) and t asc t asc(max) . 11: assumes that t cp t cp(max) and t asc 3 t asc(max) . 12: t off(max) and t oez (max) defines the time at which the output achieves the high impedance state (i out ?0 ? ) and is not reference to v oh(min) or v ol(max) . switching characteristics (ta=0~70?c, v cc =5v?0%, vss=0v, unless otherwise noted, see notes 6,13,14) limits min max parameter access time from cas access time from ras columu address access time symbol t cac unit min max min max ns ns ns ns ns ns 5 15 30 35 15 60 t rac t aa t cpa t oea t clz access time from cas precharge output low impedance time from cas low output disable time after cas high (note 7,8) (note 7,9) (note 7,10) (note 7,11) (note 7) (note 12) 5 t off t oez (note 12) (note 7) output disable time after oe high access time from oe 15 15 5 13 25 30 13 50 13 13 ns ns 20 35 40 70 20 20 20 m5m44260c-5,-5s m5m44260c-6,-6s m5m44260c-7,-7s capacitance limits min max unit typ pf pf pf input capacitance, address inputs c i (a) c i (clk) c i / o symbol parameter test conditions input capacitance, clock inputs input/output capacitance, data ports 5 7 v i =v ss f=1mhz v i =25mvrms 7 (ta=0~70?c , v cc =5v?0%, v ss =0v, unless otherwise noted)
fast page mode 4194304-bit (262144-word by 16-bit) dynamic ram m5m44260cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44260cj,tp-5,-5s : under development 5 read and refresh cycles note 21: either t rch or t rrh must be satisfied for a read cycle. limits min max parameter read cycle time ras low pulse width cas low pulse width symbol t rc unit min max min max ns ns ns ns ns ns t ras t cas t csh t rsh t rcs cas hold time after ras low read setup time before cas low read hold time after cas high (note 21) t rch t rrh ns ns t ral t och t orh ras hold time after cas low read hold time after ras high column address to ras hold time cas hold time after oe low ras hold time after oe low ns ns ns 10000 10000 10000 10000 10000 10000 0 0 90 50 13 50 13 0 25 13 13 0 0 110 60 15 60 15 0 30 15 15 0 0 130 70 20 70 20 0 35 20 20 (note 21) m5m44260c-5,-5s m5m44260c-6,-6s m5m44260c-7,-7s limits min max parameter refresh cycle time ras high pulse width delay time, ras low to cas low symbol t ref unit min max min max ms ns ns ns ns ns t rp t rcd t crp t rpc t cpn delay time, cas high to ras low delay time, ras high to cas low cas high pulse width (note 19) (note 15) (note 16) (note 17) ns ns ns ns ns ns t rad t asr t asc t rah t cah t t column address delay time from ras low row address setup time before ras low column address setup time before cas low row address hold time after ras low column address hold time after cas low transition time timing requirements (for read, write, read-modify-write, refresh and fast-page mode cycles) (note 18) (note 18) delay time, data to cas low delay time, data to oe low delay time, cas high to data delay time, oe high to data t dzc t dzo t cdd t odd 50 35 0 30 10 50 20 5 10 15 10 15 0 0 1 0 0 20 45 30 10 50 37 25 0 40 7 50 18 5 10 13 8 13 0 0 1 0 50 20 5 10 15 0 0 0 13 13 10 15 0 1 0 0 15 15 ns ns ns ns note 13: the timing requirements are assumed t t =5ns. 14: v ih(min) and v il(max) are reference levels for measuring timing of input signals. 15: t rcd(max) is specified as a reference point only. if t rcd is less than t rcd(max) , access time is t rac . if t rcd is greater than t rcd(max ), access time is controlled exclusively by t cac or t aa . 16: t rad(max) is specified as a reference point only. if t rad 3 t rad(max) and t asc t asc(max ), access time is controlled exclusively by t aa . 17: t asc(max) is specified as a reference point only. if t rcd 3 t rcd(max) and t asc 3 t asc(max) , access time is controlled exclusively by t cac . 18: either t dzc or t dzo must be satisfied. 19: either t cdd or t odd must be satisfied. 20: t t is measured between v ih(min) and v il(max) . (ta=0~70?c, v cc =5v?0%, v ss =0v, unless otherwise noted, see notes 6,13,14) 20 (note 19) (note 20) m5m44260c-5,-5s m5m44260c-6,-6s m5m44260c-7,-7s 8.2 8.2 8.2 ms t ref refresh cycle time * 128 128 128
fast page mode 4194304-bit (262144-word by 16-bit) dynamic ram m5m44260cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44260cj,tp-5,-5s : under development 6 read-write and read-modify-write cycles note 22: t rwc is specified as t rwc(min) = t rac(max) + t odd(min) + t rwl(min) + t rp(min) +4 t t . 23: t wcs , t cwd , t rwd and t awd and t cpwd are specified as reference points only. if t wcs 3 t wcs(min) the cycle is an early write cycle and the dq pins will remain high impedance throughout the entire cycle. if t cwd 3 t cwd(min) , t rwd 3 t rwd(min) , t awd 3 t awd(min) and t cpwd 3 t cpwd(min) (for fast page mode cycle only), the cycle is a read-modify-write cycle and the dq will contain the data read from the selected address. if neither of the above condition (delayed write) of the dq (at access time and until cas or oe goes back to v ih ) is indeterminate. limits min max parameter read write/read modify write cycle time ras low pulse width cas low pulse width symbol t rwc unit min max min max ns ns ns ns ns ns t ras t cas t csh t rsh t rcs cas hold time after ras low ras hold time after cas low read setup time before cas low (note 22) (note 23) ns ns ns ns ns t cwd t rwd t awd t cwl t rwl delay time, cas low to w low delay time, ras low to w low delay time, address to w low write pulse width data setup time before cas low or w low data hold time after cas low or w low oe hold time after w low t wp t ds t dh t oeh 15 13 20 ns ns ns ns cas hold time after w low ras hold time after w low 10000 10000 10000 10000 10000 55 100 55 100 0 35 15 15 80 50 10 0 10 150 49 49 0 31 13 13 68 43 8 0 8 126 86 86 70 120 70 120 0 45 20 20 95 60 15 0 180 15 (note 23) (note 23) m5m44260c-5,-5s m5m44260c-6,-6s m5m44260c-7,-7s write cycle (early write and delayed write) limits min max parameter write cycle time ras low pulse width cas low pulse width symbol t wc unit min max min max ns ns ns ns ns ns t ras t cas t csh t rsh t wcs cas hold time after ras low write setup time before cas low write hold time after cas low (note 23) t wch t cwl ns ns t rwl t wp t ds ras hold time after cas low cas hold time after w low ns ns ns 10000 10000 10000 10000 10000 10000 ns ns 8 0 90 50 13 50 13 13 13 8 0 8 13 10 0 110 60 15 60 15 15 15 10 0 10 15 t dh t oeh ras hold time after w low oe hold time after w low data setup time before cas low or w low data hold time after cas low or w low write pulse width 15 0 130 70 20 70 20 20 15 0 15 20 20 m5m44260c-5,-5s m5m44260c-6,-6s m5m44260c-7,-7s 10000
fast page mode 4194304-bit (262144-word by 16-bit) dynamic ram m5m44260cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44260cj,tp-5,-5s : under development 7 fast-page mode cycle (read, early write, read -write, read-modify-write cycle) (note 24) note 24: all previously specified timing requirements and switching characteristics are applicable to their respective fast page mode cycle. 25: t ras(min) is specified as two cycles of cas input are performed. 26: t cp(max) is specified as a reference point only. limits min parameter fast page mode read/write cycle time ras low pulse width for read or write cycle cas high pulse width symbol t pc unit min max min max ns ns ns ns ns ns t prwc t ras t cp t cprh t cpwd ras hold time after cas precharge (note 25) (note 26) delay time, cas precharge to w low (note 23) fast page mode read write/read modify write cycle time 30 35 85 8 48 71 15 100000 40 45 115 10 65 95 35 40 100 10 55 80 m5m44260c-5,-5s m5m44260c-6,-6s m5m44260c-7,-7s 15 100000 max 12 100000 cbr self refresh ras low pulse width t rass ? t rps t chs 100 100 110 -50 100 90 -50 130 -50 cbr self refresh ras high precharge time cbr self refresh cas hold time self refresh cycle * (note 28) cas before ras refresh cycle, extended refresh cycle * (note 27) limits min max parameter cas setup time before ras low symbol t csr unit min max min max ns ns t chr 5 10 cas hold time after ras low 5 10 5 15 note 27: eight or more cas before ras cycles instead of eight ras cycles are necessary for proper operation of cas before ras refresh mode. m5m44260c-5,-5s m5m44260c-6,-6s m5m44260c-7,-7s limits min max parameter symbol unit min max min max ns ns ns 20 20 25 t cas cas low pulse width m5m44260c-5,-5s m5m44260c-6,-6s m5m44260c-7,-7s
fast page mode 4194304-bit (262144-word by 16-bit) dynamic ram m5m44260cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44260cj,tp-5,-5s : under development 8 timing diagrams (note 29) read cycle t crp t asr t rah t rad t rcd t csh t asc t cah t rcs t ras t rc t rsh t cas t ral t cac t aa t clz t rac t off t rch t rrh t asr t rp hi-z hi-z row address data valid note 29 indicates the don't care input. v ih(min) v in v ih(max) or v il(min) v in v il(max) indicates the invalid output. t dzc hi-z t oez t odd t oea t och t dzo t cdd t orh t rpc t crp lcas/ucas dq 1 ~dq 16 (inputs) ras w dq 1 ~dq 16 (outputs) oe a 0 ~a 8 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il row address column address
fast page mode 4194304-bit (262144-word by 16-bit) dynamic ram m5m44260cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44260cj,tp-5,-5s : under development byte read cycle t crp t asr t rah t rad t rcd t csh t asc t cah t rcs t ras t rc t rsh t cas t ral t rac t rch t rrh t asr t rp hi-z t oez t odd t oea t och t dzo t orh t cac t aa t clz t off hi-z hi-z t dzc hi-z t cdd 9 t rpc t crp t cpn ucas (or lcas) dq 1 ~dq 8 (or dq 9 ~dq 16 ) (inputs) lcas (or ucas) dq 1 ~dq 8 (or dq 9 ~dq 16 ) (outputs) dq 9 ~dq 16 (or dq 1 ~dq 8 ) (inputs) dq 9 ~dq 16 (or dq 1 ~dq 8 ) (outputs) ras w oe a 0 ~a 8 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol row address row address data valid column address
fast page mode 4194304-bit (262144-word by 16-bit) dynamic ram m5m44260cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44260cj,tp-5,-5s : under development write cycle (early write) t crp t asr t rah t rcd t csh t asc t cah t wcs t ras t wc t rsh t cas t wch t asr t rp hi-z column address row address data valid t ds t dh 10 t rpc t crp t cpn lcas/ucas dq 1 ~dq 16 (inputs) ras w dq 1 ~dq 16 (outputs) oe a 0 ~a 8 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il row address
fast page mode 4194304-bit (262144-word by 16-bit) dynamic ram m5m44260cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44260cj,tp-5,-5s : under development byte write cycle (early write) t crp t asr t rah t rcd t csh t asc t cah t wcs t ras t wc t rsh t cas t wch t asr t rp hi-z column address row address data valid t ds t dh hi-z 11 t rpc t crp t cpn ucas (or lcas) dq 1 ~dq 8 (or dq 9 ~dq 16 ) (inputs) lcas (or ucas) dq 1 ~dq 8 (or dq 9 ~dq 16 ) (outputs) dq 9 ~dq 16 (or dq 1 ~dq 8 ) (inputs) dq 9 ~dq 16 (or dq 1 ~dq 8 ) (outputs) ras w oe a 0 ~a 8 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol row address
fast page mode 4194304-bit (262144-word by 16-bit) dynamic ram m5m44260cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44260cj,tp-5,-5s : under development write cycle (delayed write) t crp t asr t rah t rcd t csh t asc t cah t rcs t ras t wc t rsh t cas t asr t rp hi-z row address data valid t clz t wch t cwl t rwl t dh t ds hi-z hi-z t wp t dzc t oez t dzo t odd t oeh 12 t rpc t crp t cpn lcas/ucas dq 1 ~dq 16 (inputs) ras w dq 1 ~dq 16 (outputs) oe a 0 ~a 8 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il row address column address
fast page mode 4194304-bit (262144-word by 16-bit) dynamic ram m5m44260cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44260cj,tp-5,-5s : under development byte write cycle (delayed write) t crp t asr t rah t rcd t csh t asc t cah t rcs t ras t wc t rsh t cas t asr t rp hi-z column address row address data valid t clz t wch t cwl t rwl t dh t ds hi-z hi-z t dzc t oez t dzo t odd t oeh hi-z 13 t rpc t crp t cpn ucas (or lcas) dq 1 ~dq 8 (or dq 9 ~dq 16 ) (inputs) lcas (or ucas) dq 1 ~dq 8 (or dq 9 ~dq 16 ) (outputs) dq 9 ~dq 16 (or dq 1 ~dq 8 ) (inputs) dq 9 ~dq 16 (or dq 1 ~dq 8 ) (outputs) ras w oe a 0 ~a 8 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t wp row address
fast page mode 4194304-bit (262144-word by 16-bit) dynamic ram m5m44260cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44260cj,tp-5,-5s : under development read-write, read-modify-write cycle t crp t asr t rah t rcd t csh t asc t cah t rcs t ras t rwc t rsh t cas t asr t rp hi-z column address row address data valid t clz t cwl t rwl t dh t ds hi-z hi-z t wp t dzc t oez t dzo t odd t oeh t awd t cwd t rwd data valid t aa t cac t rac t oea t rad 14 t rpc t crp lcas/ucas dq 1 ~dq 16 (inputs) ras w dq 1 ~dq 16 (outputs) oe a 0 ~a 8 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il row address
fast page mode 4194304-bit (262144-word by 16-bit) dynamic ram m5m44260cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44260cj,tp-5,-5s : under development byte read-write, read-modify-write cycle t crp t asr t rah t rcd t csh t asc t cah t rcs t ras t rwc t rsh t cas t asr t rp hi-z column address row address data valid t clz t cwl t rwl t dh t ds hi-z hi-z t wp t dzc t oez t dzo t odd t oeh t awd t cwd t rwd data valid t aa t cac t rac t oea t rad hi-z 15 t rpc t crp t cpn ucas (or lcas) dq 1 ~dq 8 (or dq 9 ~dq 16 ) (inputs) lcas (or ucas) dq 1 ~dq 8 (or dq 9 ~dq 16 ) (outputs) dq 9 ~dq 16 (or dq 1 ~dq 8 ) (inputs) dq 9 ~dq 16 (or dq 1 ~dq 8 ) (outputs) ras w oe a 0 ~a 8 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol row address
fast page mode 4194304-bit (262144-word by 16-bit) dynamic ram m5m44260cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44260cj,tp-5,-5s : under development ras-only refresh cycle t crp t asr t rah t ras t rc t asr t crp t rpc t rp row address hi-z 16 lcas/ucas dq 1 ~dq 16 (inputs) ras w dq 1 ~dq 16 (outputs) oe a 0 ~a 8 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il row address
fast page mode 4194304-bit (262144-word by 16-bit) dynamic ram m5m44260cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44260cj,tp-5,-5s : under development cas before ras refresh cycle, extended refresh cycle * t ras t rc t asr t crp t rpc t rp row column address address t rpc t rc t ras t csr t chr t csr t rpc t cpn t rch t rcs t off hi-z t oez t rp t chr t cdd t odd hi-z 17 lcas/ucas dq 1 ~dq 16 (inputs) ras w dq 1 ~dq 16 (outputs) oe a 0 ~a 8 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il
fast page mode 4194304-bit (262144-word by 16-bit) dynamic ram m5m44260cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44260cj,tp-5,-5s : under development 18 hidden refresh cycle (read) (note 30) note 30: early write, delayed write, read write or read modify write cycle is applicable instead of read cycle. timing requirements and output state are the same as that of each cycle described above. t crp t asr t rah t rad t rcd t cah t rcs t ras t rc t chr t cac t aa t clz t rac t off t rrh t asr t rp hi-z column address row address data valid t ras t rc t rp t rsh t asc t ral hi-z t dzc t cdd hi-z t dzo t oea t orh t odd t oez lcas/ucas dq 1 ~dq 16 (inputs) ras w dq 1 ~dq 16 (outputs) oe a 0 ~a 8 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il row address
fast page mode 4194304-bit (262144-word by 16-bit) dynamic ram m5m44260cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44260cj,tp-5,-5s : under development fast page mode read cycle t crp t asr t rah t rad t rcd t cah t rcs t ras t cp t cac t aa t clz t rac t off hi-z row address t asr t rp t cas t asc hi-z t dzc t dzo t oea t och t csh t pc t cas t cp t cas t rsh t cah t asc t cah t asc t rch t rcs t rch t rch t rrh t dzc t cdd hi-z t off t aa data valid-2 t clz t cac data valid-3 t aa t clz t cac t off t cpa t oez t och t oea t cpa t oea t oez t odd t och t orh t dzo t odd t oez t dzo t odd t dzc t rcs t cprh hi-z hi-z hi-z 19 lcas/ucas dq 1 ~dq 16 (inputs) ras w dq 1 ~dq 16 (outputs) oe a 0 ~a 8 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il row address t ral data valid-1 column address1 column address3 column address2
fast page mode 4194304-bit (262144-word by 16-bit) dynamic ram m5m44260cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44260cj,tp-5,-5s : under development fast page mode byte read cycle t crp t asr t rah t rad t rcd t cah t ras t cp t cac t aa t clz t rac t off t asr hi-z column row address data valid-1 t rp t cas t asc hi-z t dzo t oea t och t csh t pc t cas t cp t cas t rsh column t cah t asc t cah t rch t rch t ral t rch t dzc t dzc t cdd hi-z t off t aa data valid-2 t clz t cac data valid-3 t aa t clz t cac t off t cpa t oez t och t oea t cpa t oea t oez t odd t och t orh t dzo t odd t oez t dzo t odd address1 address2 hi-z t cprh t asc 20 row address ucas (or lcas) dq 1 ~dq 8 (or dq 9 ~dq 16 ) (inputs) lcas (or ucas) dq 1 ~dq 8 (or dq 9 ~dq 16 ) (outputs) dq 9 ~dq 16 (or dq 1 ~dq 8 ) (inputs) dq 9 ~dq 16 (or dq 1 ~dq 8 ) (outputs) ras w oe a 0 ~a 8 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol column address3 t rcs t rrh t rcs t dzc t rcs
fast page mode 4194304-bit (262144-word by 16-bit) dynamic ram m5m44260cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44260cj,tp-5,-5s : under development fast page mode write cycle (early write) t crp t asr t rah t rcd t cah t wcs t ras t cp t asr hi-z t rp t cas t asc t csh t pc t cas t cp t cas address column row address row column address2 column t cah t asc t cah t asc t wch t rsh t wch t wcs t wcs t wch data valid-1 data valid-2 data valid-3 t ds t dh t ds t dh t ds t dh address1 address3 21 lcas/ucas dq 1 ~dq 16 (inputs) ras w dq 1 ~dq 16 (outputs) oe a 0 ~a 8 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il
fast page mode 4194304-bit (262144-word by 16-bit) dynamic ram m5m44260cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44260cj,tp-5,-5s : under development fast page mode byte write cycle (early write) t crp t asr t rah t rcd t cah t wcs t ras t cp t asr hi-z t rp t cas t asc t csh t pc t cas t cp t cas t rsh address row address row t cah t asc t cah t asc t wch t wch t wcs t wcs t wch data valid-1 data valid-2 data valid-3 t ds t dh t ds t dh t ds t dh hi-z column column address2 column address1 address3 22 ucas (or lcas) dq 1 ~dq 8 (or dq 9 ~dq 16 ) (inputs) lcas (or ucas) dq 1 ~dq 8 (or dq 9 ~dq 16 ) (outputs) dq 9 ~dq 16 (or dq 1 ~dq 8 ) (inputs) dq 9 ~dq 16 (or dq 1 ~dq 8 ) (outputs) ras w oe a 0 ~a 8 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol
fast page mode 4194304-bit (262144-word by 16-bit) dynamic ram m5m44260cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44260cj,tp-5,-5s : under development fast-page mode write cycle (delayed write) t crp t asr t rah t rcd t cah t ras t cp t asr hi-z t rp t cas t asc t csh t pc t cas t rsh address column row address row t cah t asc t rcs t wch data valid-1 t dzc t ds column t rwl t cwl t wp t rcs t wp t cwl hi-z hi-z t dh t ds t dzc t wch data valid-2 t dh hi-z hi-z t clz t clz t dzo t oez t odd t dzo t oez t odd t oeh address1 address2 23 lcas/ucas dq 1 ~dq 16 (inputs) ras w dq 1 ~dq 16 (outputs) oe a 0 ~a 8 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il
fast page mode 4194304-bit (262144-word by 16-bit) dynamic ram m5m44260cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44260cj,tp-5,-5s : under development fast-page mode byte write cycle (delayed write) t crp t asr t rah t rcd t cah t ras t cp t asr hi-z t rp t cas t asc t csh t pc t cas t rsh address row address row t cah t asc t rcs t wch data valid-1 t dzc t ds t rwl t cwl t wp t rcs t wp t cwl hi-z hi-z t dh t ds t dzc t wch data valid-2 t dh hi-z hi-z t clz t clz t dzo t oez t odd t dzo t oez t odd t oeh hi-z 24 ucas (or lcas) dq 1 ~dq 8 (or dq 9 ~dq 16 ) (inputs) lcas (or ucas) dq 1 ~dq 8 (or dq 9 ~dq 16 ) (outputs) dq 9 ~dq 16 (or dq 1 ~dq 8 ) (inputs) dq 9 ~dq 16 (or dq 1 ~dq 8 ) (outputs) ras w oe a 0 ~a 8 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol column address2 column address1
fast page mode 4194304-bit (262144-word by 16-bit) dynamic ram m5m44260cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44260cj,tp-5,-5s : under development fast page mode read-write, read-modify-write cycle t crp t asr t rah t rcd t cah t ras t cp t asr hi-z t rp t cas t asc t csh t prwc t cas t rwl address column row address row t cah t asc t rcs t rwd data valid-1 t dzc t ds t cwl t wp t rcs t wp t cwl hi-z hi-z t dh t ds t dzc t cpwd data valid-2 t dh hi-z hi-z t clz t dzo t oez t odd t dzo t oez t oeh t rad t cwd t awd t awd t cwd t aa t cac data valid-1 t aa t cac data valid-2 t clz t rac t oea t cpa t oea t odd address1 25 lcas/ucas dq 1 ~dq 16 (inputs) ras w dq 1 ~dq 16 (outputs) oe a 0 ~a 8 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il column address2
fast page mode 4194304-bit (262144-word by 16-bit) dynamic ram m5m44260cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44260cj,tp-5,-5s : under development fast page mode byte read-write, read-modify-write cycle t crp t asr t rah t rcd t cah t ras t cp t asr hi-z t rp t cas t asc t csh t prwc t cas t rwl address row address row t cah t asc t rwd data valid-1 t ds t cwl t wp t wp t cwl hi-z hi-z t ds t cpwd data valid-2 t dh hi-z hi-z t clz t dzo t oez t odd t dzo t oez t oeh t rad t cwd t awd t awd t cwd t cac data valid-1 t aa t cac data valid-2 t clz t rac t oea t cpa t oea t odd hi-z t dzc 26 ucas (or lcas) dq 1 ~dq 8 (or dq 9 ~dq 16 ) (inputs) lcas (or ucas) dq 1 ~dq 8 (or dq 9 ~dq 16 ) (outputs) dq 9 ~dq 16 (or dq 1 ~dq 8 ) (inputs) dq 9 ~dq 16 (or dq 1 ~dq 8 ) (outputs) ras w oe a 0 ~a 8 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol column column address1 address2 t rcs t rcs t dh t dzc t aa
fast page mode 4194304-bit (262144-word by 16-bit) dynamic ram m5m44260cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44260cj,tp-5,-5s : under development self refresh cycle * (note28) t rpc t rps t asr t crp row column address address t rass t csr t cpn t rch t rcs t off hi-z t oez t rp t chs t rpc hi-z t cdd t odd 27 lcas/ucas dq 1 ~dq 16 (inputs) ras w dq 1 ~dq 16 (outputs) oe a 0 ~a 8 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il
fast page mode 4194304-bit (262144-word by 16-bit) dynamic ram m5m44260cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44260cj,tp-5,-5s : under development switching from read/write operation to self refresh operation. the time interval from the falling edge of ras signal in the last cbr refresh cycle during read/write operation period to the falling edge of ras signal at the start of self refresh operation should be set within t nsd (shown in table 2). note 28 : self refresh sequence two refreshing methods should be used properly depending on the low pulse width (t rass ) of ras signal during self refresh period. 1. distributed refresh during read/write operation (a) timing diagram read / write cycle self refresh cycle read / write cycle t nsd t rass 3 100? t snd last refresh cycle first refresh cycle table 2 definition of cbr distributed refresh (including extended refresh) switching from self refresh operation to read/write operation. the time interval from the rising edge of ras signal at the end of self refresh operation to the falling edge of ras signal in the first cbr refresh cycle during read/write operation period should be set within t snd (shown in table 2). switching from read/write operation to self refresh operation. the time interval t nsd from the falling edge of ras signal in the last ras only refresh cycle during read/write operation period to the falling edge of ras signal at the start of self refresh operation should be set within 16?. switching from self refresh operation to read/write operation. the time interval t snd from the rising edge of ras signal at the end of self refresh operation to the falling edge of ras signal in the first cbr refresh cycle during read/write operation period should be set within 16?. ras read / write cycle cbr distributed refresh ras only distributed refresh read / write self refresh t nsd 16? t snd 16? (b) definition of distributed refresh t ref t ref / 512 refresh cycle read/write cycles ras t ref / 512 read/write cycles refresh cycle refresh cycle note: hidden refresh may be used instead of cbr refresh. ras/cas refresh may be used instead of ras only refresh. 28 1.1 cbr distributed refresh 1.2 ras only distributed refresh the cbr distributed refresh performs more than 512 constant period (250? max.) cbr cycles within 128 ms. all combinations of nine row address signals (a 0 ~a 8 ) are selected during 512 constant period (16? max.) ras only refresh cycles within 8.2 ms. definition of ras only distributed refresh t nsd 250? t snd 250? self refresh read / write
fast page mode 4194304-bit (262144-word by 16-bit) dynamic ram m5m44260cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44260cj,tp-5,-5s : under development all combination of nine row address signals (a 0 ~a 8 ) are selected during 512 continuous ras only refresh cycles within 8.2 ms. 2. burst refresh during read/write operation (a) timing diagram read / write self refresh read / write t nsb t rass 3 100? t snb last refresh cycles first refresh cycles table 3 read / write cycle cbr burst refresh ras only burst refresh t nsb +t snb 8.2ms definition of cbr burst refresh switching from read/write operation to self refresh operation. the time interval t nsb from the falling edge of ras signal in the first cbr refresh cycle during read/write operation period to the falling edge of ras signal at the start of self refresh operation should be set within 8.2 ms. switching from self refresh operation to read/write operation. the time interval t snb from the rising edge of ras signal at the end of self refresh operation to the falling edge of ras signal in the last cbr refresh cycle during read/write operation period should be set within 8.2 ms. switching from read/write operation to self refresh operation. the time interval from the falling edge of ras signal in the first ras only refresh cycle during read/write operation period to the falling edge of ras signal at the start of self refresh operation should be set within t nsb (shown in table 3). switching from self refresh operation to read/write operation. the time interval from the rising edge of ras signal at the end of self refresh operation to the falling edge of ras signal in the last ras only refresh cycle during read/write operation period should be set within t snb (shown in table 3). ras refresh cycles 511 cycles refresh cycles 511 cycles (b) definition of burst refresh 8.2ms read/write cycles ras refresh cycles 512 cycles 2.2 ras only burst refresh 2.1 cbr burst refresh the cbr burst refresh performs more than 512 continuous cbr cycles within 8.2 ms. definition of ras only burst refresh 29 t snb 8.2ms t nsb 8.2ms read / write self refresh self refresh read / write

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